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19-5303; Rev 0; 6/10
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
General Description
The MAX2063 high-linearity, dual digital variable-gain amplifier (VGA) operates in the 50MHz to 1000MHz frequency range. Each digital attenuator is controlled as a slave peripheral using either the SPIK-compatible interface or a 5-bit parallel bus with 31dB total adjustment range in 1dB steps. An added feature allows "rapid-fire" gain selection between each of four steps, preprogrammed by the user through the SPI-compatible interface. A separate 2-pin control allows the user to quickly access any one of four customized attenuation states without reprogramming the SPI bus. Since each of the stages has its own external RF input and RF output, this component can be configured to either optimize noise figure (amplifier configured first) or OIP3 (amplifier configured last). The device's performance features include 24dB of amplifier gain (amplifier only), 5.6dB noise figure (NF) at maximum gain (including attenuator insertion losses), and a high OIP3 level of +41dBm. Each of these features makes the device an ideal VGA for multipath receiver and transmitter applications. In addition, the device operates from a single +5V supply with full performance, or a +3.3V supply for an enhanced power-savings mode with lower performance. This device is available in a compact 48-pin thin QFN package (7mm x 7mm) with an exposed pad. Electrical performance is guaranteed over the extended temperature range, from TC = -40NC to +85NC.
Features
S Independently Controlled Dual Paths S 50MHz to 1000MHz RF Frequency Range S Pin-Compatible Family Includes MAX2062 (Analog/Digital VGA) MAX2064 (Analog-Only VGA) S 21.3dB (typ) Maximum Gain S 0.25dB Gain Flatness Over 100MHz Bandwidth S 31dB Gain Range S 58dB Path Isolation at 200MHz S Supports Four "Rapid-Fire" Preprogrammed Attenuator States Quickly Access Any One of Four Customized Attenuation States Without Reprogramming the SPI Bus Ideal for Fast-Attack, High-Level Blocker Protection Prevents ADC Overdrive Condition S Excellent Linearity at 200MHz +41dBm OIP3 +56dBm OIP2 +19dBm Output 1dB Compression Point
S 5.6dB Typical Noise Figure S 25ns Digital Switching Time S Very Low Distortion VGA Amplitude Overshoot/
MAX2063
Undershoot of 0.05dB
S Single +5V Supply (or +3.3V Operation) S Amplifier Power-Down Mode for TDD Applications
Applications
IF and RF Gain Stages Temperature-Compensation Circuits Cellular Band WCDMA and cdma2000M Base Stations GSM 850/GSM 900 EDGE Base Stations WiMAXK and LTE Base Stations and Customer Premise Equipment Fixed Broadband Wireless Access Wireless Local Loop Military Systems
SPI is a trademark of Motorola, Inc. cdma2000 is a registered trademark of Telecommunications Industry Association. WiMAX is a trademark of WiMAX Forum.
Ordering Information
PART MAX2063ETM+ MAX2063ETM+T TEMP RANGE -40NC to +85NC -40NC to +85NC PIN-PACKAGE 48 Thin QFN-EP* 48 Thin QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. T = Tape and reel.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA MAX2063
ABSOLUTE MAXIMUM RATINGS
VCC_AMP_1, VCC_AMP_2, VCC_RG to GND ..........-0.3V STA_A_1, STA_A_2, STA_B_1, STA_B_2, PD_1, PD_2, AMPSET ................................................-0.3V DAT, CS, CLK, DA_SP .........................................-0.3V D0_1, D1_1, D2_1, D3_1, D4_1, D0_2, D1_2, D2_2, D3_2, D4_2 ............................................-0.3V AMP_IN_1, AMP_IN_2 .......................................+0.95V AMP_OUT_1, AMP_OUT_2 ..................................-0.3V D_ATT_IN_1, D_ATT_IN_2, D_ATT_OUT_1, D_ATT_OUT_2 ..................................................... 0V REG_OUT .............................................................-0.3V to +5.5V to +3.6V to +3.6V to +3.6V to +1.2V to +5.5V to +3.6V to +3.6V RF Input Power (D_ATT_IN_1, D_ATT_IN_2) ............... +20dBm RF Input Power (AMP_IN_1, AMP_IN_2)...................... +18dBm qJC (Notes 1, 2) ......................................................... +12.3NC/W qJA (Notes 2, 3) ............................................................ +38NC/W Continuous Power Dissipation (Note 1) ..............................5.3W Operating Case Temperature Range (Note 4) .. -40NC to +85NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
Note 1: Based on junction temperature TJ = TC + (BJC x VCC x ICC). This formula can be used when the temperature of the exposed pad is known while the device is soldered down to a PCB. See the Applications Information section for details. The junction temperature must not exceed +150NC. Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Note 3: Junction temperature TJ = TA + (BJA x VCC x ICC). This formula can be used when the ambient temperature of the PCB is known. The junction temperature must not exceed +150NC. Note 4: TC is the temperature on the exposed pad of the package. TA is the ambient temperature of the device and PCB.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
+5V SUPPLY DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = +4.75V to +5.25V, AMPSET = 0, PD_1 = PD_2 = 0, TC = -40NC to +85NC. Typical values are at VCC_ = +5.0V and TC = +25NC, unless otherwise noted.) PARAMETER Supply Voltage Supply Current Power-Down Current Input Low Voltage Input High Voltage Input Logic Current SYMBOL VCC IDC IDCPD VIL VIH IIH, IIL 1.7 -1 PD_1 = PD_2 = 1, VIH = 3.3V CONDITIONS MIN 4.75 TYP 5 148 5.2 MAX 5.25 205 8 0.5 3.465 +1 UNITS V mA mA V V FA
+3.3V SUPPLY DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = +3.135V to +3.465V, AMPSET = 1, PD_1 = PD_2 = 0, TC = -40NC to +85NC. Typical values are at VCC_ = +3.3V and TC = +25NC, unless otherwise noted.) PARAMETER Supply Voltage Supply Current Power-Down Current Input Low Voltage Input High Voltage SYMBOL VCC IDC IDCPD VIL VIH 1.7 PD_1 = PD_2 = 1, VIH = 3.3V CONDITIONS MIN 3.135 TYP 3.3 88 4.3 MAX 3.465 145 8 0.5 3.465 UNITS V mA mA V V
2
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
RECOMMENDED AC OPERATING CONDITIONS
PARAMETER RF Frequency SYMBOL fRF (Note 5) CONDITIONS MIN 50 TYP MAX 1000 UNITS MHz
MAX2063
+5V SUPPLY AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = +4.75V to +5.25V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz fRF 500MHz, TC = -40NC to +85NC. Typical values are at maximum gain setting, VCC_ = +5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6) PARAMETER SYMBOL fRF = 50MHz fRF = 100MHz fRF = 200MHz Small-Signal Gain G fRF = 350MHz, TC = +25NC fRF = 450MHz fRF = 750MHz fRF = 900MHz Gain vs. Temperature From 100MHz to 200MHz Gain Flatness vs. Frequency Any 100MHz frequency band from 200MHz to 500MHz fRF = 50MHz fRF = 100MHz fRF = 200MHz Noise Figure NF fRF = 350MHz fRF = 450MHz fRF = 750MHz fRF = 900MHz Total Attenuation Range Output Second-Order Intercept Point (Minimum Attenuation) OIP2 POUT = 0dBm/tone, Df = 1MHz, f1 + f2 RF input 1 amplified power measured at RF output 2 relative to RF output 1, all unused ports terminated to 50I RF input 2 amplified power measured at RF output 1 relative to RF output 2, all unused ports terminated to 50I 18 CONDITIONS MIN TYP 22.0 21.7 21.3 21.0 20.8 19.9 18.3 -0.006 0.35 0.25 5.2 5.4 5.6 5.8 5.9 6.4 6.7 30.8 51.6 dB dBm dB dB dB/NC 23 dB MAX UNITS
48.8 dB 49.4
Path Isolation
3
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA MAX2063
+5V SUPPLY AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = +4.75V to +5.25V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz fRF 500MHz, TC = -40NC to +85NC. Typical values are at maximum gain setting, VCC_ = +5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6) PARAMETER SYMBOL CONDITIONS POUT = 0dBm/tone, Df = 1MHz, fRF = 50MHz POUT = 0dBm/tone, Df = 1MHz, fRF = 100MHz POUT = 0dBm/tone, Df = 1MHz, fRF = 200MHz Output Third-Order Intercept Point OIP3 POUT = 0dBm/tone, Df = 1MHz, fRF = 350MHz POUT = 0dBm/tone, Df = 1MHz, fRF = 450MHz POUT = 0dBm/tone, Df = 1MHz, fRF = 750MHz POUT = 0dBm/tone, Df = 1MHz, fRF = 900MHz Output -1dB Compression Point Second Harmonic Third Harmonic Group Delay Amplifier Power-Down Time Amplifier Power-Up Time Input Return Loss Output Return Loss Insertion Loss Input Second-Order Intercept Point Input Third-Order Intercept Point Attenuation Range Step Size Relative Attenuation Accuracy Absolute Attenuation Accuracy 0dB to 16dB Insertion Phase Step fRF = 170MHz 0dB to 24dB 0dB to 31dB RLIN RLOUT IL IIP2 IIP3 PRF1 = 0dBm PRF2 = 0dBm (minimum attenuation), Df = 1MHz, f1 + f2 PIN1 = 0dBm PIN2 = 0dBm (minimum attenuation), Df = 1MHz P1dB HD2 HD3 (Note 7) POUT = +3dBm POUT = +3dBm Includes EV kit PCB delays PD_1 or PD_2 from 0 to 1, amplifier DC supply current settles to within 0.1mA PD_1 or PD_2 from 1 to 0, amplifier DC supply current settles to within 1% 50I source 50I load MIN TYP 47.1 43.9 41.0 37.0 35.2 28.7 26.5 18.8 -54.8 -72.9 0.87 0.5 0.5 23.3 24.4 3.0 53.1 43.2 30.8 1 0.11 0.23 -0.4 0.6 0.9 Degrees dBm dBc dBc ns Fs Fs dB dB dB dBm dBm dB dB dB dB dBm MAX UNITS
DIGITAL ATTENUATOR (each path, unless otherwise noted)
4
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
+5V SUPPLY AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = +4.75V to +5.25V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz fRF 500MHz, TC = -40NC to +85NC. Typical values are at maximum gain setting, VCC_ = +5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6) PARAMETER Amplitude Overshoot/ Undershoot Switching Speed Input Return Loss Output Return Loss Maximum Clock Speed Data-to-Clock Setup Time Data-to-Clock Hold Time Clock-to-CS Setup Time CS Positive Pulse Width CS Setup Time Clock Pulse Width RLIN RLOUT fCLK tCS tCH tES tEW tEWS tCW SYMBOL Between any two states RF settled to within Q0.1dB 50I source 50I load CONDITIONS Elapsed time = 15ns Elapsed time = 40ns 31dB to 0dB 0dB to 31dB MIN TYP 1.0 0.05 25 21 21.6 21.2 20 2 2.5 3 7 3.5 5 MAX UNITS dB ns dB dB MHz ns ns ns ns ns ns
MAX2063
SERIAL PERIPHERAL INTERFACE (SPI)
+3.3V SUPPLY AC ELECTRICAL CHARACTERISTIC
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = +3.3V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 1, PD_1 = PD_2 = 0, 100MHz fRF 500MHz, TC = -40NC to +85NC. Typical values are at maximum gain setting, VCC_ = +3.3V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6) PARAMETER Small-Signal Gain Output Third-Order Intercept Point Noise Figure Total Attenuation Range RF input 1 amplified power measured at RF output 2 relative to RF output 1, all unused ports terminated to 50I RF input 2 amplified power measured at RF output 1 relative to RF output 2, all unused ports terminated to 50I P1dB (Note 7) SYMBOL G OIP3 NF POUT = 0dBm/tone CONDITIONS MIN TYP 20.9 29.6 5.9 30.8 48.8 dB 49.1 13.4 dBm MAX UNITS dB dBm dB dB
Path Isolation
Output -1dB Compression Point
Note 5: Operation outside this range is possible, but with degraded performance of some parameters. See the Typical Operating Characteristics. Note 6: All limits include external component losses. Output measurements are performed at the RF output port of the Typical Application Circuit. Note 7: It is advisable not to continuously operate RF input 1 or RF input 2 above +15dBm.
5
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA MAX2063
Typical Operating Characteristics
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5V, attenuators are set for maximimum gain, RF ports are driven from 50 sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. VCC
MAX2063 toc01
GAIN vs. RF FREQUENCY
MAX2063 toc02
GAIN vs. RF FREQUENCY
MAX2063 toc03
170 TC = -40C SUPPLY CURRENT (mA) 160
24 TC = -40C 22 GAIN (dB)
24
22
GAIN (dB)
VCC = 4.75V, 5.00V, 5.25V
TC = +25C 150
20 TC = +85C 18 TC = +25C
20
140 TC = +85C 130 4.750 4.875 5.000 VCC (V) 5.125 5.250
18
16 50 250 450 650 850 1050 RF FREQUENCY (MHz)
16 50 250 450 650 850 1050 RF FREQUENCY (MHz)
GAIN OVER ATTENUATOR SETTING vs. RF FREQUENCY
MAX2063 toc04
ATTENUATOR RELATIVE ERROR vs. RF FREQUENCY
MAX2063 toc05
ATTENUATOR ABSOLUTE ERROR vs. RF FREQUENCY
0.75
ABSOLUTE ERROR (dB)
MAX2063 toc06
25 GAIN OVER ATTENUATOR SETTING (dB)
1.00 0.75 RELATIVE ERROR (dB) 0.50 0.25 0 -0.25 -0.50 -0.75 ERROR FROM 23dB TO 24dB
1.00
15
0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 24dB 50 250 450 650 850 1050 RF FREQUENCY (MHz) 25dB
5
-5
-15 50 250 450 650 850 1050 RF FREQUENCY (MHz)
-1.00 50 250 450 650 850 1050 RF FREQUENCY (MHz)
INPUT MATCH OVER ATTENUATOR SETTING vs. RF FREQUENCY
OUTPUT MATCH OVER ATTENUATOR SETTING (dB)
MAX2063 toc07
OUTPUT MATCH OVER ATTENUATOR SETTING vs. RF FREQUENCY
MAX2063 toc08
INPUT MATCH OVER ATTENUATOR SETTING (dB)
0 -10 -20 -30 2dB -40 31dB -50 0 200 400 600 800 16dB 8dB
0
0dB
-10 16dB, 31dB -20 2dB
1dB
4dB
-30 0dB -40 0
1dB, 4dB, 8dB
1000
200
400
600
800
1000
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
6
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5V, attenuators are set for maximimum gain, RF ports are driven from 50 sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25C, unless otherwise noted.)
REVERSE GAIN OVER ATTENUATOR SETTING vs. RF FREQUENCY
MAX2063 toc09
MAX2063
ATTENUATOR PHASE CHANGE BETWEEN STATES (DEGREES)
ATTENUATOR PHASE CHANGE BETWEEN STATES vs. RF FREQUENCY
50 40 30 20 10 0 -10 -20 -30 50 250 450 650 850 1050 RF FREQUENCY (MHz) 25 REFERENCED TO HIGH GAIN STATE POSITIVE PHASE = ELECTRICALLY SHORTER
MAX2063 toc10
CHANNEL ISOLATION vs. RF FREQUENCY (MAXIMUM GAIN)
RELATIVE POWERS AT RF OUTPUTS CHANNEL ISOLATION (dB) 65 55 45 35 CH2 TO CH1
MAX2063 toc11
REVERSE GAIN OVER ATTENUATOR SETTING (dB)
-30 -40 -50 ATTEN 31dB -60 -70 -80 50 250 450 650 850
60
75
ATTEN 0dB
CH1 TO CH2
1050
50
250
450
650
850
1050
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
CHANNEL ISOLATION vs. RF FREQUENCY (MINIMUM GAIN)
MAX2063 toc12
NOISE FIGURE vs. RF FREQUENCY
MAX2063 toc13
NOISE FIGURE vs. RF FREQUENCY
MAX2063 toc14
75 RELATIVE POWERS AT RF OUTPUTS CHANNEL ISOLATION (dB) 65 55 45 35 CH2 TO CH1 25 50 250 450 650 850 CH1 TO CH2
9 8 NOISE FIGURE (dB) 7 6 5 4 3 TC = -40C TC = +85C
9 8 NOISE FIGURE (dB) 7 6 5 4 3 VCC = 4.75V, 5.00V, 5.25V
TC = +25C
1050
50
250
450
650
850
1050
50
250
450
650
850
1050
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
OUTPUT P1dB vs. RF FREQUENCY
MAX2063 toc15
OUTPUT P1dB vs. RF FREQUENCY
MAX2063 toc16
22 20
OUTPUT P1dB (dBm)
22 20
OUTPUT P1dB (dBm)
TC = -40C
VCC = 5.25V
18 TC = +85C 16 14 12 50 250 450 650 850 1050 RF FREQUENCY (MHz)
18 VCC = 4.75V 16 14 12 50 250 450 650 850 1050 RF FREQUENCY (MHz) VCC = 5.00V
TC = +25C
7
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA MAX2063
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5V, attenuators are set for maximimum gain, RF ports are driven from 50 sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25C, unless otherwise noted.)
OUTPUT IP3 vs. RF FREQUENCY
MAX2063 toc17
OUTPUT IP3 vs. RF FREQUENCY
MAX2063 toc18
OUTPUT IP3 vs. ATTENUATOR STATE
POUT = 0dBm/TONE RF = 350MHz TC = -40C, LSB, USB OUTPUT IP3 (dBm) 40
MAX2063 toc19
50 POUT = 0dBm/TONE 45 OUTPUT IP3 (dBm) 40 35 30 25 20 50 250 450 650 850 TC = +85C TC = -40C TC = +25C
50 45 OUTPUT IP3 (dBm) 40 35 30 25 20 VCC = 5.00V POUT = 0dBm/TONE
45
VCC = 5.25V
VCC = 4.75V
35
TC = +25C, LSB, USB TC = +85C, LSB, USB
30 50 250 450 650 850 1050 0 4 8 12 16 20 24 28 RF FREQUENCY (MHz) ATTENUATOR STATE (dB)
1050
RF FREQUENCY (MHz)
2ND HARMONIC vs. RF FREQUENCY
MAX2063 toc20
2ND HARMONIC vs. RF FREQUENCY
MAX2063 toc21
2ND HARMONIC vs. ATTENUATOR STATE
TC = +85C 60 2ND HARMONIC (dBc) 55 50 45 40 POUT = 3dBm RF = 350MHz
MAX2063 toc22
70
POUT = 3dBm
70 VCC = 5.25V 2ND HARMONIC (dBc) 60
POUT = 3dBm
65
2ND HARMONIC (dBc)
60
TC = +85C
VCC = 5.00V 50
50 TC = -40C 40 TC = +25C 30 50 250 450 650 850 1050 RF FREQUENCY (MHz)
TC = -40C
40
VCC = 4.75V
TC = +25C
30 50 250 450 650 850 1050 RF FREQUENCY (MHz)
0
4
8
12
16
20
24
28
ATTENUATOR STATE (dB)
3RD HARMONIC vs. RF FREQUENCY
MAX2063 toc23
3RD HARMONIC vs. RF FREQUENCY
POUT = 3dBm VCC = 5.25V VCC = 5.00V
MAX2063 toc24
3RD HARMONIC vs. ATTENUATOR STATE
TC = -40C 3RD HARMONIC (dBc) 75 POUT = 3dBm RF = 350MHz
MAX2063 toc25
100 90 3RD HARMONIC (dBc) TC = -40C 80
POUT = 3dBm
100 90 3RD HARMONIC (dBc) 80 70 VCC = 4.75V 60 50
80
TC = +25C 70 TC = +85C 60 50 50 250 450 650 850 1050 RF FREQUENCY (MHz)
70
TC = +85C
TC = +25C
65 50 250 450 650 850 1050 0 4 8 12 16 20 24 28 RF FREQUENCY (MHz) ATTENUATOR STATE (dB)
8
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5V, attenuators are set for maximimum gain, RF ports are driven from 50 sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25C, unless otherwise noted.)
MAX2063
OUTPUT IP2 vs. RF FREQUENCY
MAX2063 toc26
OUTPUT IP2 vs. RF FREQUENCY
MAX2063 toc27
OUTPUT IP2 vs. ATTENUATOR STATE
TC = +85C 55 OUTPUT IP2 (dBm) POUT = 0dBm/TONE RF = 350MHz
MAX2063 toc28
70 TC = +85C 60 OUTPUT IP2 (dBm) 50 TC = +25C 40 30 20 50 250 450 TC = -40C
POUT = 0dBm/TONE
70 60 OUTPUT IP2 (dBm) 50 40 30 20 VCC = 4.75V VCC = 5.25V
60
POUT = 0dBm/TONE
VCC = 5.00V
50 TC = -40C TC = +25C 45
40 50 250 450 650 850 1050 0 4 8 12 16 20 24 28 RF FREQUENCY (MHz) ATTENUATOR STATE (dB)
650
850
1050
RF FREQUENCY (MHz)
GAIN vs. RF FREQUENCY (ATTENUATOR ONLY)
MAX2063 toc29
GAIN vs. RF FREQUENCY (ATTENUATOR ONLY)
MAX2063 toc30
0 -1 -2 -3 -4 -5 50 250 450 650 850 TC = -40C TC = +25C
0 -1 -2 -3 -4 -5 VCC = 4.75V, 5.00V, 5.25V
GAIN (dB)
TC = +85C
GAIN (dB)
1050
50
250
450
650
850
1050
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
9
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA MAX2063
Typical Operating Characteristics
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.3V, attenuators are set for maximimum gain, RF ports are driven from 50 sources, AMPSET = 1, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. VCC
MAX2063 toc31
GAIN vs. RF FREQUENCY
MAX2063 toc32
GAIN vs. RF FREQUENCY
MAX2063 toc33
120 110 SUPPLY CURRENT (mA) 100 90 80 TC = -40C TC = +25C
24 TC = -40C 22 GAIN (dB) TC = +25C
VCC = 3.3V
24
22 GAIN (dB)
VCC = 3.465V VCC = 3.3V
20 TC = +85C 18
20
VCC = 3.135V
18
70 60 3.1 3.2
TC = +85C 3.3 VCC (V) 3.4 3.5 16 50 250 450 650 850 1050 RF FREQUENCY (MHz) 16 50 250 450 650 850 1050 RF FREQUENCY (MHz)
INPUT MATCH OVER ATTENUATOR SETTING vs. RF FREQUENCY
INPUT MATCH OVER ATTENUATOR SETTING (dB)
MAX2063 toc34
OUTPUT MATCH OVER ATTENUATOR SETTING vs. RF FREQUENCY
OUTPUT MATCH OVER ATTENUATOR SETTING (dB) VCC = 3.3V
MAX2063 toc35
0 -10 -20 -30 4dB -40 31dB -50 50 250 450 650
VCC = 3.3V 16dB 8dB 0dB
0
-10 16dB, 31dB -20 2dB 1dB
2dB 1dB
-30 4dB -40 50 250 0dB 450
8dB
850
1050
650
850
1050
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
NOISE FIGURE vs. RF FREQUENCY
MAX2063 toc36
VCC = 3.3V TC = +85C
8 NOISE FIGURE (dB) 7 6 5 4 3 2 50
8 VCC = 3.135V NOISE FIGURE (dB) 7 6 5 4 3 VCC = 3.465V VCC = 3.3V
TC = +25C TC = -40C
250
450
650
850
1050
2 50 250 450 650 850 1050 RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
10
MAX2063 toc37
9
NOISE FIGURE vs. RF FREQUENCY
9
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.3V, attenuators are set for maximimum gain, RF ports are driven from 50 sources, AMPSET = 1, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25C, unless otherwise noted.)
MAX2063
OUTPUT P1dB vs. RF FREQUENCY
MAX2063 toc38
TC = +25C 14 OUTPUT P1dB (dBm) 12 10 8 6 50 250 450 650 TC = +85C
VCC = 3.3V TC = -40C
MAX2063 toc39
POUT = 0dBm/TONE VCC = 3.3V TC = -40C
14 OUTPUT P1dB (dBm) 12 10 8 6 50 250 450
VCC = 3.3V VCC = 3.465V
40 OUTPUT IP3 (dBm)
30 TC = +25C 20
VCC = 3.135V 10 650 850 1050 50 250
TC = +85C
850
1050
450
650
850
1050
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
OUTPUT IP3 vs. RF FREQUENCY
MAX2063 toc41
OUTPUT IP3 vs. ATTENUATOR STATE
MAX2063 toc42
2ND HARMONIC vs. RF FREQUENCY
VCC = 3.3V POUT = 3dBm
MAX9888 toc43
50
POUT = 0dBm/TONE
34 32 OUTPUT IP3 (dBm) 30 28 26 TC = +85C LSB, USB 24 TC = -40C LSB, USB
80 70
2ND HARMONIC (dBc)
40 OUTPUT IP3 (dBm) VCC = 3.465V 30 VCC = 3.135V 20
VCC = 3.3V POUT = 0dBm/TONE RF = 350MHz
60 TC = +25C 50 40 TC = -40C 30 20
TC = +85C
TC = +25C LSB, USB
VCC = 3.3V
10 50 250 450 650 850 1050 RF FREQUENCY (MHz)
22 0 4 8 12 16 20 24 28 ATTENUATOR STATE (dB)
50
250
450
650
850
1050
RF FREQUENCY (MHz)
2ND HARMONIC vs. RF FREQUENCY
MAX9888 toc44
2ND HARMONIC vs. ATTENUATOR STATE
VCC = 3.3V POUT = 3dBm RF = 350MHz
TC = +85C TC = +25C
MAX2063 toc45
80 70 2ND HARMONIC (dBc) 60 50 VCC = 3.465V
POUT = 3dBm
80 70
2ND HARMONIC (dBc)
60 50 40
VCC = 3.3V 40 30 20 50 250 450 650 850 1050 RF FREQUENCY (MHz) VCC = 3.135V
TC = -40C 30 0 4 8 12 16 20 24 28 ATTENUATOR STATE (dB)
11
MAX2063 toc40
16
OUTPUT P1dB vs. RF FREQUENCY
16 50
OUTPUT IP3 vs. RF FREQUENCY
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA MAX2063
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.3V, attenuators are set for maximimum gain, RF ports are driven from 50 sources, AMPSET = 1, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25C, unless otherwise noted.)
3RD HARMONIC vs. RF FREQUENCY
MAX2063 toc46
3RD HARMONIC vs. RF FREQUENCY
POUT = 3dBm
MAX2063 toc47
80
VCC = 3.3V POUT = 3dBm TC = -40C TC = +25C
80
3RD HARMONIC (dBc)
3RD HARMONIC (dBc)
70
70
VCC = 3.465V VCC = 3.135V
60
60
50
TC = +85C
50
VCC = 3.3V
40 50 250 450 650 850 1050 RF FREQUENCY (MHz)
40 50 250 450 650 850 1050 RF FREQUENCY (MHz)
3RD HARMONIC vs. ATTENUATOR STATE
MAX2063 toc48
OUTPUT IP2 vs. RF FREQUENCY
TC = +85C 60 OUTPUT IP2 (dBm) 50 40 TC = +25C 30 TC = -40C 20 VCC = 3.3V POUT = 0dBm/TONE
MAX2063 toc49
70
3RD HARMONIC (dBc)
65
TC = -40C
VCC = 3.3V POUT = 3dBm RF = 350MHz
70
60 TC = +25C 55 TC = +85C 50 0 4 8 12 16 20 24 28 ATTENUATOR STATE (dB)
50
250
450
650
850
1050
RF FREQUENCY (MHz)
OUTPUT IP2 vs. RF FREQUENCY
MAX2063 toc50
OUTPUT IP2 vs. ATTENUATOR STATE
POUT = 0dBm/TONE RF = 350MHZ VCC = 3.3V
MAX2063 toc51
70 60 OUTPUT IP2 (dBm) VCC = 3.465V 50 40 30
POUT = 0dBm/TONE
70
60 OUTPUT IP2 (dBm)
TC = +85C
VCC = 3.3V
50 TC = -40C 40
TC = +25C
VCC = 3.135V 20 50 250 450 650 850 1050 RF FREQUENCY (MHz) 30 0 4 8 12 16 20 24 28 ATTENUATOR STATE (dB)
12
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Pin Configuration
AMP_OUT_1 AMP_OUT_2 AMP_IN_1
MAX2063
PD_1
PD_2
GND
GND
GND
36 35 34 33 32 31 30 29 28 27 26 25 VCC_AMP_1 GND GND GND GND D4_1 D_ATT_OUT_1 D3_1 D2_1 D1_1 D0_1 GND 37 38 39 40 41 42 43 44 45 46 47 48 DIGITAL ATTENUATOR 1 SPI DIGITAL ATTENUATOR 2 EXPOSED PAD ACTIVE BIAS
AMP AMP
GND
TOP VIEW
AMP_IN_2
REG_OUT
AMPSET
24 ACTIVE BIAS 23 22 21 20 19 18 17 16 15 14 13 1 GND 2 D_ATT_IN_1 3 STA_A_1 4 STA_B_1 5 DAT 6 CLK 7 CS 8 VCC_RG 9 STA_B_2 10 11 12 STA_A_2 D_ATT_IN_2 GND
VCC_AMP_2 GND GND DA_SP GND D4_2 D_ATT_OUT_2 D3_2 D2_2 D1_2 D0_2 GND
MAX2063
+
THIN QFN (7mm O 7mm)
Pin Description
PIN 1, 12, 13, 20, 22, 23, 25, 28, 33, 36, 38-41, 48 2 3 NAME FUNCTION
GND
Ground
D_ATT_IN_1 STA_A_1
5-Bit Digital Attenuator RF Input (50I), Path 1. Requires a DC-blocking capacitor. Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 1 State A State B Digital Attenuator 1 Logic = 0 Logic = 0 Preprogrammed State 1 Logic = 1 Logic = 0 Preprogrammed State 2 Logic = 0 Logic = 1 Preprogrammed State 3 Logic = 1 Logic = 1 Preprogrammed State 4 SPI Data Digital Input SPI Clock Digital Input SPI Chip-Select Digital Input
4 5 6 7
STA_B_1 DAT CLK CS
13
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA MAX2063
Pin Description (continued)
PIN 8 NAME VCC_RG FUNCTION Regulator Supply Input. Connect to a 3.3V or 5V external power supply. VCC_RG powers all circuits except for the driver amplifiers. Bypass with a 10nF capacitor as close as possible to the pin. Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 2 State A State B Digital Attenuator 2 Logic = 0 Logic = 0 Preprogrammed State 1 Logic = 1 Logic = 0 Preprogrammed State 2 Logic = 0 Logic = 1 Preprogrammed State 3 Logic = 1 Logic = 1 Preprogrammed State 4 5-Bit Digital Attenuator Input (50I), Path 2. Requires a DC-blocking capacitor. 1dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable 2dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable 4dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable 8dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable 5-Bit Digital Attenuator Output (50I), Path 2. Requires a DC-blocking capacitor. Connect to AMP_IN_2 through a 1000pF capacitor. 16dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable. Digital Attenuator Serial/Parallel Control Select. Set DA_SP to 1 to select serial control. Set DA_SP to 0 to select parallel control. Driver Amplifier Supply Voltage Input, Path 2. Bypass with a 10nF capacitor as close as possible to the pin. Driver Amplifier Input (50I), Path 2. Connect to D_ATT_OUT_2 through a 1000pF capacitor. Power-Down, Path 2. See Table 2 for operation details. Driver Amplifier Output (50I), Path 2. Connect a pullup inductor from AMP_OUT_2 to VCC_. Regulator Output. Bypass with a 1FF capacitor. Driver Amplifier Bias Setting for 3.3V Operation. Set to logic 1 for 3.3V on pins VCC_AMP1 and VCC_AMP2. Set to logic 0 for 5V. Driver Amplifier Output (50I), Path 1. Connect a pullup inductor from AMP_OUT_1 to VCC_. Power-Down, Path 1. See Table 2 for operation details. Driver Amplifier Input (50I), Path 1. Connect to D_ATT_OUT_1 through a 1000pF capacitor. Driver Amplifier Supply Voltage Input, Path 1. Bypass with a 10nF capacitor as close as possible to the pin. 16dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable, path 1. 5-Bit Digital Attenuator Output (50I), Path 1. Requires a DC-blocking capacitor. Connect to AMP_IN_1 through a 1000pF capacitor. 8dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable. 4dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable. 2dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable. 1dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable. Exposed Pad. Internally connected to GND. Connect to a large PCB ground plane for proper RF performance and enhanced thermal dissipation.
9
STA_B_2
10 11 14 15 16 17 18 19 21 24 26 27 29 30 31 32 34 35 37 42 43 44 45 46 47 --
STA_A_2 D_ATT_IN_2 D0_2 D1_2 D2_2 D3_2 D_ATT_OUT_2 D4_2 DA_SP VCC_AMP_2 AMP_IN_2 PD_2 AMP_OUT_2 REG_OUT AMPSET AMP_OUT_1 PD_1 AMP_IN_1 VCC_AMP_1 D4_1 D_ATT_OUT_1 D3_1 D2_1 D1_1 D0_1 EP
14
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Detailed Description
The MAX2063 high-linearity digital VGA is a generalpurpose, high-performance amplifier designed to interface with 50I systems operating in the 50MHz to 1000MHz frequency range. Each channel of the device integrates one digital attenuator to provide 31dB of total gain control, as well as a driver amplifier optimized to provide high gain, high output IP3, low NF, and low power consumption. Each digital attenuator is controlled as a slave peripheral using either the SPI-compatible interface or a 5-bit parallel bus with 31dB total adjustment range in 1dB steps. An added feature allows "rapid-fire" gain selection between each of four steps, preprogrammed by the user through the SPI-compatible interface. A separate 2-pin control allows the user to quickly access any one of four customized attenuation states without reprogramming the SPI bus. Because each of the two stages in the separate signal paths has its own RF input and RF output, this component can be configured to either optimize NF (amplifier configured first) or OIP3 (amplifier configured last). The device's performance features include 24dB of amplifier gain (amplifier only), 5.6dB NF at maximum gain (includes attenuator insertion losses), and a high OIP3 level of +41dBm. Each of these features makes the device an ideal VGA for multipath receiver and transmitter applications. The device integrates two 5-bit digital attenuators to achieve a high level of dynamic range. Each digital attenuator has a 31dB control range, a 1dB step size, and can be programmed either through a dedicated 5-bit parallel bus or through the 3-wire SPI. See the Applications Information section and Table 1 for attenuator programming details. The attenuators can be used for both static and dynamic power control. The device includes two high-performance drivers with a fixed gain of 24dB. Each driver amplifier circuit is optimized for high linearity for the 50MHz to 1000MHz frequency range.
Table 1. Control Logic
DA_SP 0 1 DIGITAL ATTENUATOR Parallel controlled SPI controlled (control voltages show up on the parallel control pins)
MAX2063
Table 2. Operating Modes
RESULT All on AMP1 off AMP2 on AMP1 on AMP2 off All off VCC_ (V) 5 3.3 5 3.3 5 3.3 5 3.3 AMPSET 0 1 0 1 0 1 0 1 PD_1 0 0 1 1 0 0 1 1 PD_2 0 0 0 0 1 1 1 1
Applications Information
The device features an optional +3.3V supply voltage operation with reduced linearity performance. The AMPSET pin needs to be biased accordingly in each mode, as listed in Table 2. In addition, the driver amplifiers can be shut down independently to conserve DC power. See the biasing scheme outlined in Table 2 for details. The attenuators can be programmed through the 3-wire SPI/MICROWIREK-compatible serial interface using 5-bit words. Fifty-six bits of data are shifted in MSB first and framed by CS. The first 28 bits set the first attenuator, and the following 28 bits set the second attenuator. When CS is low, the clock is active and data is shifted on the rising edge of the clock. When CS transitions high, the data is latched and the attenuator setting changes (Figure 1). See Table 3 for details on the SPI data format.
Operating Modes
5-Bit Digital Attenuator Control
SPI Interface and Attenuator Settings
Driver Amplifiers
MICROWIRE is a trademark of National Semiconductor Corp.
15
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA MAX2063
D0:D7 D8:D12 1st Digital Attenuator Programming Reserved. Set to logic 0. Preprogrammed Attenuation State 1 D8 = 1dB bit, D9 = 2dB bit, D10 = 4dB bit, D11 = 8dB bit, D12 = 16dB bit D13:D17 Preprogrammed Attenuation State 2 D13 = 1dB bit, D14 = 2dB bit, D15 = 4dB bit, D16 = 8dB bit, D17 = 16dB bit D18:D22 Preprogrammed Attenuation State 3 D18 = 1dB bit, D19 = 2dB bit, D20 = 4dB bit, D21 = 8dB bit, D22 = 16dB bit D23:D27 Preprogrammed Attenuation State 4 D23 = 1dB bit, D24 = 2dB bit, D25 = 4dB bit, D26 = 8dB bit, D27 = 16dB bit D51:D55 D46:D50 D41:D45 D28:D35 D36:D40 2nd Digital Attenuator Programming Reserved. Set to logic 0. Preprogrammed Attenuation State 1 D36 = 1dB bit, D37 = 2dB bit, D38 = 4dB bit, D39 = 8dB bit, D40 = 16dB bit Preprogrammed Attenuation State 2 D41 = 1dB bit, D42 = 2dB bit, D43 = 4dB bit, D44 = 8dB bit, D45 = 16dB bit Preprogrammed Attenuation State 3 D46 = 1dB bit, D47 = 2dB bit, D48 = 4dB bit, D49 = 8dB bit, D50 = 16dB bit Preprogrammed Attenuation State 4 D51 = 1dB bit, D52 = 2dB bit, D53 = 4dB bit, D54 = 8dB bit, D55 = 16dB bit
MSB DATA DN D(N-1) D1 D0
LSB
CLOCK tCW CS tCS tCH
tES tEWS tEW NOTES: DATA ENTERED ON CLOCK RISING EDGE. ATTENUATOR REGISTER STATE CHANGE ON CS RISING EDGE. N = NUMBER OF DATA BITS.
Figure 1. SPI Timing Diagram
16
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Table 3. SPI Data Format
FUNCTION BIT D55 (MSB) 2nd Digital Attenuator State 4 D54 D53 D52 D51 D50 2nd Digital Attenuator State 3 D49 D48 D47 D46 D45 2nd Digital Attenuator State 2 D44 D43 D42 D41 D40 2nd Digital Attenuator State 1 D39 D38 D37 D36 D35 D34 D33 Reserved D32 D31 D30 D29 D28 D27 1st Digital Attenuator State 4 D26 D25 D24 D23 D22 1st Digital Attenuator State 3 D21 D20 D19 D18 D17 1st Digital Attenuator State 2 D16 D15 D14 D13 16dB step (MSB of the 5-bit word used to program the digital attenuator state 4) 8dB step 4dB step 2dB step 1dB step 16dB step (MSB of the 5-bit word used to program the digital attenuator state 3) 8dB step 4dB step 2dB step 1dB step 16dB step (MSB of the 5-bit word used to program the digital attenuator state 2) 8dB step 4dB step 2dB step 1dB step 17 Bits D[35:28] are reserved. Set to logic 0. 8dB step 4dB step 2dB step 1dB step 16dB step (MSB of the 5-bit word used to program the digital attenuator state 3) 8dB step 4dB step 2dB step 1dB step 16dB step (MSB of the 5-bit word used to program the digital attenuator state 2) 8dB step 4dB step 2dB step 1dB step 16dB step (MSB of the 5-bit word used to program the digital attenuator state 1) 8dB step 4dB step 2dB step 1dB step DESCRIPTION 16dB step (MSB of the 5-bit word used to program the digital attenuator state 4)
MAX2063
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA MAX2063
Table 3. SPI Data Format (continued)
FUNCTION BIT D12 1st Digital Attenuator State 1 D11 D10 D9 D8 D7 D6 D5 Reserved D4 D3 D2 D1 D0 (LSB) Bits D[7:0] are reserved. Set to logic 0. 8dB step 4dB step 2dB step 1dB step DESCRIPTION 16dB step (MSB of the 5-bit word used to program the digital attenuator state 1)
To capitalize on its fast 25ns switching capability, the device offers a supplemental 5-bit parallel control interface for each attenuator. The two buses of the digital logic attenuator-control pins (D0_ _-D4_ _) enable the attenuator stages (Table 4). Direct access to these 5-bit buses enables the user to avoid any programming delays associated with the SPI interface. One of the limitations of any SPI bus is the speed at which commands can be clocked into each peripheral device. By offering direct access to the 5-bit parallel interface, the user can quickly shift between digital attenuator states as needed for critical "fastattack" automatic gain-control (AGC) applications. Note that when the digital attenuators are controlled by the SPI bus, the control voltages of each digital attenuator show on the five parallel control pins (pins 14-17, 19 for digital attenuator 2, and pins 42, 44-47 for digital attenuator 1). When the digital attenuators are in SPI mode, the parallel control pins must be open.
Digital Attenuator Settings Using the Parallel Control Bus
the delays associated with reprogramming the device through the SPI bus. The switching speed is comparable to that achieved using the supplemental 5-bit parallel buses. However, by employing this specific feature, the digital attenuator I/O is further reduced by a factor of either 5 or 2.5 (5 control bits vs. 1 or 2, respectively), depending on the number of states desired. The user can employ the STA_A_1 and STA_B_1 (STA_A_2 and STA_B_2 for attenuator 2) logic input pins to apply each step as required (see Tables 5 and 6). Toggling just the STA_A_1 pin (1 control bit) yields two preprogrammed attenuation states; toggling both the STA_A_1 and STA_B_1 pins together (2 control bits) yields four preprogrammed attenuation states. As an example, assume that the AGC application requires a static attenuation adjustment to trim out gain inconsistencies within a receiver lineup. The same AGC circuit can also be called upon to dynamically attenuate an unwanted blocker signal that could desense the receiver and lead to an ADC overdrive condition. In this example, the device would be preprogrammed (through the SPI bus) with two customized attenuation states--one to address the static gain-trim adjustment, the second to counter the unwanted blocker condition. Toggling just the STA_A_1 control bit enables the user to switch quickly between the static and dynamic attenuation settings with only one I/O pin.
The device has an added feature that provides "rapid-fire" gain selection between four preprogrammed attenuation steps. As with the supplemental 5-bit buses previously mentioned, this "rapid-fire" gain selection allows the user to quickly access any one of four customized digital attenuation states without incurring
"Rapid-Fire" Preprogrammed Attenuation States
18
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
If desired, the user can also program two additional attenuation states by using the STA_B_1 control bit as a second I/O pin. These two additional attenuation settings are useful for software-defined radio applications where multiple static gain settings are needed to account for different frequencies of operation, or where multiple dynamic attenuation settings are needed to account for different blocker levels (as defined by multiple wireless standards). The sequence to be used is: 1) 2) Power supply Control lines The pin configuration of the device is optimized to facilitate a very compact physical layout of the device and its associated discrete components. The exposed pad (EP) of the device's 48-pin thin QFN-EP package provides a low thermal-resistance path to the die. It is important that the PCB on which the device is mounted be designed to conduct heat from the EP. In addition, provide the EP with a low inductance path to electrical ground. The EP MUST be soldered to a ground plane on the PCB, either directly or through an array of plated via holes. Table 7 lists typical application circuit component values.
Layout Considerations
MAX2063
Power-Supply Sequencing
Table 4. Digital Attenuator Settings (Parallel Control, DA_SP = 0)
INPUT D0_ _ D1_ _ D2_ _ D3_ _ D4_ _ LOGIC = 0 (OR GROUND) Disable 1dB attenuator Disable 2dB attenuator Disable 4dB attenuator Disable 8dB attenuator Disable 16dB attenuator LOGIC = 1 Enable 1dB attenuator Enable 2dB attenuator Enable 4dB attenuator Enable 8dB attenuator Enable 16dB attenuator
Table 5. Programmed Attenuation State Settings for Attenuator 1 (DA_SP = 1)
STA_A_1 0 1 0 1 STA_B_1 0 0 1 1 SETTING FOR DIGITAL ATTENUATOR 1* Preprogrammed attenuation state 1 Preprogrammed attenuation state 2 Preprogrammed attenuation state 3 Preprogrammed attenuation state 4
*Defined by SPI programming bits D8:D27 (see Table 3 for details).
Table 6. Programmed Attenuation State Settings for Attenuator 2 (DA_SP = 1)
STA_A_2 0 1 0 1 STA_B_2 0 0 1 1 SETTING FOR DIGITAL ATTENUATOR 2* Preprogrammed attenuation state 1 Preprogrammed attenuation state 2 Preprogrammed attenuation state 3 Preprogrammed attenuation state 4
*Defined by SPI programming bits D36:D55 (see Table 3 for details).
19
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA MAX2063
Table 7. Typical Application Circuit Component Values
DESIGNATION C1, C2, C6, C8, C9, C13 C4, C7, C11, C14, C16 C15 L1, L2 U1 QTY 6 5 1 2 1 DECRIPTION 1000pF capacitors (0402) Murata GRM1555C1H102J 10nF capacitors (0402) Murata GRM155R71E103K 1mF capacitor (0603) Murata GRM188R71C105K 820nH inductors (1008) Coilcraft 1008CS-821XJLC VGA (48-pin thin QFN-EP, 7mm x 7mm) Maxim MAX2063ETM+ COMPONENT SUPPLIER Murata North America Electronics, Inc. Murata North America Electronics, Inc. Murata North America Electronics, Inc. Coilcraft, Inc. Maxim Integrated Products, Inc.
20
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Typical Application Circuit
RF OUTPUT 1 C6 L1 C15 C7 C14 RF OUTPUT 2 C13 L2
MAX2063
VCC
AMP_OUT_1
AMP_OUT_2
AMP_IN_1
AMP_IN_2
REG_OUT
AMPSET
PD_1
PD_2
GND
GND
GND
VCC C4 C2
36 35 34 33 32 31 30 29 28 27 26 25 VCC_AMP_1 GND GND GND GND D4_1 D_ATT_OUT_1 D3_1 D2_1 D1_1 D0_1 GND 37 38 39 40 41 42 43 44 45 46 47 48 DIGITAL ATTENUATOR 1 SPI DIGITAL ATTENUATOR 2 EXPOSED PAD ACTIVE BIAS
AMP AMP
GND
24 ACTIVE BIAS 23 22 21 20 19 18 17 16 15 14 13 1 GND 2 D_ATT_IN_1 3 STA_A_1 4 STA_B_1 5 DAT 6 CLK 7 CS 8 VCC_RG 9 STA_B_2 10 11 12 STA_A_2 D_ATT_IN_2 GND
VCC_AMP_2 GND GND DA_SP GND D4_2 D_ATT_OUT_2 D3_2 D2_2 D1_2 D0_2 GND
VCC C11 C9
MAX2063
+
C1 RF INPUT 1
VCC C16
C8 RF INPUT 2
Chip Information
PROCESS: SiGe BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 48 Thin QFN-EP PACKAGE CODE T4877+7 OUTLINE NO. 21-0144 LAND PATTERN NO. 90-0133
21
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA MAX2063
Revision History
REVISION NUMBER 0 REVISION DATE 6/10 Initial release DESCRIPTION PAGES CHANGED --
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22
(c)
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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